• C A S T
    Hardware Accelerated Systems Lab

    We aim to advance modern computer systems based on specialized hardware in the post-Moore’s law era. We conduct research in various fields of hardware design such as computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory with holistic design approach to improve overall system performance. Our current mission is to build a high-performance and scalable computing platform for future AI applications.

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AI Chip

Machine learning (ML) becomes the hottest computing paradigm as it revolutionizes how computers handle cognitive tasks based on a massive amount of observed data.

Datacenter SoC

Cloud computing is rapidly changing how enterprises run their services by offering a virtualized computing infrastructure over the internet. Datacenter is a power house ...

Memory-Centric Computing

Traditionally CPU that executes arithmetic and logic calculation is the center of the computing systems while a few layers of memory are built around it to feed the data.

Secure Hardware Platform for Internet-of-Things

Internet-of-Things (IoT) connects billions of physical objects by harnessing them wireless communication with embedded electronics.

52

Journal & Conference Papers

400K

USD Grants Received

14

Research Members

Selected Publications

Please see the following selected publications to learn more about CastLab’s research.

  • A Cloud-Scale Acceleration Architecture, International Symposium on Microarchitecture (MICRO) 2016 link

  • Toward Accelerating Deep Learning at Scale Using Specialized Logic, Hot Chips: A Symposium on High Performance Chips (HOTCHIPS) 2015 link

  • A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services, International Symposium on Computer Architecture (ISCA) 2014 link

  • A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor with Bio-Inspired Neural Perception Engine, IEEE Journal of Solid-State Circuits (JSSC) 2010 link

  • Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-aware Task Pipelining, IEEE Micro 2009 link

Research Partners

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