[VLSI 2025] Jung-Hoon Kim’s paper on Adelia: A 4nm LLM Accelerator with Streamlined Dataflow and Dual-Mode Parallelization for Efficient Generative AI Inference is accepted

Congratulations!

We have a paper accepted to IEEE Symposium on VLSI Technology and Circuits (VLSI), 2025

“A 4nm LLM Accelerator with Streamlined Dataflow and Dual-Mode Parallelization for Efficient Generative AI Inference”

  • Jung-Hoon Kim, Sukbin Lim, Junseo Cha, Seungjae Moon, Dongjin Seo, Hunjong Lee, Jongho Kim, Jinwon Lee, Joo-Young Kim