3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving

Adelia: A 4-nm LLM Processing Unit with Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency

A 11.0 TOPS/W Diffusion Accelerator with Temporal Data Reuse for Real-Time Text-to-Motion Generation

SCRec: A Scalable Computational Storage System with Statistical Sharding and Tensor-train Decomposition for Recommendation Models

A 57.3 fps 12.8 TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity

An End-to-End Diffusion Accelerator With Reconfigurable Hyper-Precision and Unified Non-Matrix Processing Engine

A Quantitative Analysis of Mamba-2-based Large Language Model: Study of State Space Duality

DPIM: A 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core

SuFP: Piecewise Bit Allocation Floating-Point for Robust Neural Network Quantization

SAL-PIM: A Subarray-level Processing-in-Memory Architecture with LUT-based Linear Interpolation for Transformer-based Text Generation