[ISSCC 2025] Jaehoon Heo’s paper on HuMoniX: A 57.3 fps 12.8 TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity is accepted

Congratulations! We have a paper accepted to IEEE International Solid-State Circuits Conference (ISSCC) 2025 “HuMoniX: A 57.3 fps 12.8 TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity”

[MICRO 2024] Seungjae Yoo and Hangyeol Kim’s paper on AdapTiV: Sign-Similarity based Image-Adaptive Token Merging for Vision Transformer Acceleration is accepted

Congratulations! We have a paper accepted to ACM/IEEE International Symposium on Microarchitecture (MICRO), 2024 “AdapTiV: Sign-Similarity based Image-Adaptive Token Merging for Vision Transformer Acceleration”

[IEEE Micro 2024] Seungjae Moon’s paper on LPU: A Latency-Optimized Highly Scalable Processor for Large Language Model Inference is accepted

Congratulations! We have a paper accepted to IEEE Micro, 2024 “LPU: A Latency-Optimized Highly Scalable Processor for Large Language Model Inference”

[ICCAD 2024] Hyunjun Cho’s paper on APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits is accepted

Congratulations! We have a paper accepted to ACM/IEEE International Conference on Computer-Aided Design(ICCAD), 2024 “APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits”

[ESSERC 2024] Sungyeob Yoo’s paper on A 28nm 4.96 TOPS/W End-to-End Diffusion Accelerator with Reconfigurable Hyper-Precision and Unified Non-Matrix Processing Engine is accepted

Congratulations! We have a paper accepted to Symposium on European Solid-State Electronics Research Conference(ESSERC), 2024 “A 28nm 4.96 TOPS/W End-to-End Diffusion Accelerator with Reconfigurable Hyper-Precision and Unified Non-Matrix Processing Engine” Sungyeob Yoo, Geonwoo Ko, Seri Ham, Seeyeon Kim, Yi Chen, and Joo-Young Kim

[ESSERC 2024] Donghyuk Kim’s paper on DPIM: A 19.36TOPS/W 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core is accepted

Congratulations! We have a paper accepted to Symposium on European Solid-State Electronics Research Conference(ESSERC), 2024 “A 19.36TOPS/W 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core” Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Hoichang Jeong, Keonhee Park, Ki-soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin […]

[HotChips 2024] Sungyeob Yoo’s paper on Picasso: An Area/Energy-Efficient End-to-End Diffusion Accelerator with Hyper-Precision Data Type is accepted

Congratulations! We have a paper accepted to Symposium on High Performance Chips (HotChips), 2024 “ Picasso: An Area/Energy-Efficient End-to-End Diffusion Accelerator with Hyper-Precision Data Type” Sungyeob Yoo, Geonwoo Ko, Seri Ham, Seeyeon Kim, Yi Chen, and Joo-Young Kim

[ISCA 2024] Seunghee Han and Seungjae Moon’s paper on BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing is accepted

Congratulations! We have a paper accepted to ACM/IEEE International Symposium on Computer Architecture (ISCA), 2024 “BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing” *Seunghee Han, *Seungjae Moon, Teokkyu Suh, Jaehoon Heo and Joo-Young Kim (*equal contribution)

[JSSC 2024] Jaehoon Heo and Junghoon Kim’s paper on SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for Area/Energy-Efficient On-Device Learning is accepted

Congratulations! We have a paper accepted to IEEE Journal of Solid-State Circuits (JSSC), 2024 “SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for Area/Energy-Efficient On-Device Learning” *Jaehoon Heo, *Jung-Hoon Kim, Wontak Han, Jaeuk Kim and Joo-Young Kim (*equal contribution)

[IEEE Custom Integrated Circuits Conference (CICC), 2024] Sukbin Lim’s paper on A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection is accepted

Congratulations! We have a paper accepted to IEEE Custom Integrated Circuits Conference (CICC), 2024 “A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection” Sukbin Lim, Jaehoon Heo, Jinho Yang, Joo-Young Kim