Congratulations!
We have a paper accepted to IEEE European Solid-State Circuits Conference (ESSCIRC), 2023
” JNPU: A 1.04TFLOPS Joint-DNN Training Processor with Speculative Cyclic Quantization and Triple Heterogeneity on Microarchitecture / Precision / Dataflow ”
- Je Yang, Sukbin Lim, Sukjin Lee, Jae-Young Kim and Joo-Young Kim